1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.
2. Background Art
Conventionally, nonvolatile semiconductor memory devices such as NAND flash memories have been fabricated by two-dimensionally integrating elements on the surface of a silicon substrate. In this type of flash memory, increasing the degree of integration by downscaling is required to reduce cost per bit and increase memory capacity. However, downscaling tends to cause the problem of interference between adjacent memory cells, which leads to malfunction of memory cells. For example, data once stored in a memory cell may be erased by operation of its adjacent memory cell.
As a technique for increasing the degree of integration of a memory, for example, JP-A-2007-266143 (Kokai) proposes a technique of three-dimensionally stacking memory cells. In the technique disclosed in this publication, electrode films and dielectric films are alternately stacked on a silicon substrate to form a stacked body, and a plurality of through holes are formed in this stacked body by a single processing. A charge storage layer is formed on the side surface of the through hole, and then silicon is buried inside the through hole to form a silicon pillar. Thus, a memory cell is formed at the intersection between each electrode film and each silicon pillar, resulting in a three-dimensional arrangement of memory cells.
However, even in this type of three-dimensionally stacked memory, the electrode film and the dielectric film need to be thinned to increase the number of stacked films for higher degree of integration while restricting the aspect ratio of the through hole. Furthermore, thinning the electrode film and the dielectric film decreases the distance between memory cells arranged along the silicon pillar, and again tends to cause interference between adjacent memory cells.